Pre-Production

WM8759

w

PP Rev 3.1 June 2006

11

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCKIN

1 BCKIN

Figure 3 I

RIGHT JUSTIFIED MODE

The WM8759 supports word lengths of 16-bits in right justified mode.

In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is

time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also

used as a timing reference to indicate the beginning or end of the data words.

In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected

word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of

word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above

requirements are met.

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN

transition. LRCIN is high during the left samples and low during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

16

3

2

1

14

15

LSB

MSB

16

3

2

1

14

15

LSB

MSB

Figure 4 Right Justified Mode Timing Diagram

DSP MODE

In DSP/PCM mode, the left channel MSB is available on either the 1

edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows

left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused

BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRC output will resemble the frame pulse shown in Figure 5 and Figure 6. In

device slave mode, Figure 7 and Figure 8, it is possible to use any length of frame pulse less than 1/fs,

providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge

of the next frame pulse.