Production Data

WM8766

w

PD Rev 4.1 July 2005

27

DACPD [2:0]

DAC CHANNEL 1

DAC CHANNEL 2

DAC CHANNEL 3

000

Active

Active

Active

001

DISABLE

Active

Active

010

Active

DISABLE

Active

011

DISABLE

DISABLE

Active

100

Active

Active

DISABLE

101

DISABLE

Active

DISABLE

110

Active

DISABLE

DISABLE

111

DISABLE

DISABLE

DISABLE

Table 15 DAC Disable Control

MASTER POWERDOWN

This control bit powers down the references for the whole chip. Therefore for complete powerdown,

all DACs should be powered down first before setting this bit.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

4

PWRDNALL

0

Master Power Down Bit:

0: Not powered down

1: Powered down

MASTER MODE SELECT

Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK

and BCLK are outputs and are generated by the WM8766. In Slave mode LRCLK and BCLK are

inputs to WM8766.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

5

MS

0

DAC Audio Interface Master/Slave

Mode Select:

0: Slave mode

1: Master mode

MASTER MODE LRCLK FREQUENCY SELECT

In Master mode the WM8766 generates LRCLK and BCLK. These clocks are derived from the

master clock and the ratio of MCLK to LRCLK is set by RATE.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

8:6

RATE [2:0]

010

Master Mode

MCLK:LRCLK Ratio Select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

101: 768fs