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WM8776 데이터시트(PDF) 39 Page - Wolfson Microelectronics plc |
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WM8776 데이터시트(HTML) 39 Page - Wolfson Microelectronics plc |
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39 / 57 page ![]() Production Data WM8776 w PD Rev 4.0 April 2005 39 ADC INPUT MIXER AND POWERDOWN CONTROL REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R21 (15h) 0010101 ADC Input Mux 4:0 AMX[4:0] 00001 ADC left channel input mixer control bits (see Table 16) R13 (0Dh) 0001101 Powerdown Control 6 AINPD 0 Input mux and buffer powerdown 0: Input mux and buffer enabled 1: Input mux and buffer powered down Register bits AMX[4:0] control the left and right channel inputs into the stereo ADC. The default is AIN1. One bit of AMX is allocated to each stereo input pair to allow the signals to be mixed before being digitised by the ADC. For example, if AMX[4:0] is 00101, the input signal to the ADC will be (AIN1L+AIN3L) on the left channel and (AIN1R+AIN3R) on the right channel. However if the analogue input buffer is powered down, by setting AINPD, then all 5-channel mixer inputs are switched to buffered VMIDADC. AMX[4:0] LEFT ADC INPUT RIGHT ADC INPUT 00001 AIN1L AIN1R 00010 AIN2L AIN2R 00100 AIN3L AIN3R 01000 AIN4L AIN4R 10000 AIN5L AIN5R Table 16 ADC Input Mixer AIN1L/R AIN2L/R AIN3L/R AIN4L/R AIN5L/R AMX[0] AMX[1] AMX[2] AMX[3] AMX[4] Figure 25 ADC Input Mixer |
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