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WM8782SEDS/R 데이터시트(PDF) 12 Page - Wolfson Microelectronics plc

부품명 WM8782SEDS/R
상세설명  24-Bit, 192kHz Stereo ADC
PDF  21 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8782SEDS/R 데이터시트(HTML) 12 Page - Wolfson Microelectronics plc

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WM8782
Production Data
w
PD, August 2006, Rev 4.2
12
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 8 Right Justified Audio Interface (assuming n-bit word length)
In I
2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 9 I
2S Audio Interface (assuming n-bit word length)



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