Production Data

WM8785

w

PD Rev 4.1 December 2006

27

MASTER CLOCK FREQUENCY (MHZ)

SAMPLING RATE

(LRCLK)

OVERSAMPLING

RATIO

128fs

192fs

256fs

384fs

512fs

768fs

32kHz

Single Rate

-

-

8.192

12.288

16.384

24.576

44.1kHz

Single Rate

-

-

11.2896

16.9344

22.5792

33.8688

48kHz

Single Rate

-

-

12.288

18.432

24.576

36.864

96kHz

Dual Rate

-

-

24.576

36.864

-

-

192kHz

Quad Rate

24.576

36.864

-

-

-

-

Table 12 Slave Mode: Recommended Master Clock Frequency Selection

MLCK AND LRCLK PHASE RELATIONSHIP

The WM8785 does not require a specific phase relationship between MLCK and LRCLK. If the

relationship between MCLK and LRCLK changes by more than +/-8 BCLKs in a 64 BLCK frame, the

WM8785 will attempt to re-synchronise. During re-synchronisation, data samples may be dropped or

duplicated.

POWER DOWN CONTROL

The WM8785 can be powered down by setting the PWRDNL and PWRDNR bits. This is described in

the table below.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3

PWRDNR

0

Power Down Right Channel

0 = Power On

1 = Power Off

R2(02h)

Signal control

4

PWRDNL

0

Power Down Left Channel

0 = Power On

1 = Power Off

Table 13 Power Down Control