WM8940_07 datasheet(53/85 Pages) WOLFSON

53 / 85 page

Pre-Production

WM8940

Pre-Production, Rev 3.0, February 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of FRAME clock:

0=DAC data appear in ‘left’ phase of

FRAME

1=DAC data appears in ‘right’ phase of

FRAME

ALRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of FRAME clock:

0=ADC data appear in ‘left’ phase of

FRAME

1=ADC data appears in ‘right’ phase of

FRAME

Companding

Control

WL8

8 Bit Word Length Enable

Only recommended for use with

companding

0=Word Length controlled by WL

1=8 bits

Table 43 Audio Interface Control

Note:

Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the

device will operate in 24-bit mode.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKSEL

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

4:2

BCLKDIV

000

Configures the BCLK and FRAME output

frequency, for use when the chip is

master over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Clock

generation

control

Sets the chip to be master over FRAME

and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs

generated by the WM8940 (MASTER)

Table 44 Clock Control

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