WM8974GEFLSLASHV datasheet(63/87 Pages) WOLFSON

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Production Data

WM8974

PD Rev 4.2 March 2007

POWER MANAGEMENT

SAVING POWER BY REDUCING OVERSAMPLING RATE

The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode.

Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x

oversampling results in a slight decrease in noise performance compared to 128x but lowers the

power consumption of the device.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R10

DAC control

DACOSR128

DAC oversample rate select

0 = 64x (lowest power)

1 = 128x (best SNR)

R14

ADC control

ADCOSR128

ADC oversample rate select

0 = 64x (lowest power)

1 = 128x (best SNR)

Table 59 ADC and DAC Oversampling Rate Selection

VMID

The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance

of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the

startup time of the VMID circuit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power management

1:0

VMIDSEL

Reference string impedance to VMID pin

(detemines startup time):

00=off (open circuit)

01=75kΩ

10=300kΩ

11=2.5kΩ (for fastest startup)

Table 60 VMID Impedance Control

BIASEN

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power management

BIASEN

Analogue amplifier bias control

0=Disabled

1=Enabled

Table 61 BIASEN Control

ESTIMATED SUPPLY CURRENTS

When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from

DCVDD when DCVDD=1.8V and fs=48kHz (This will be lower at lower sample rates). When the

PLL is enabled an additional 700 microamps will be drawn from DCVDD.

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