WM9707

Production Data

w

PD Rev 4.1 June 2006

21

SLOTS 6 TO 9: SURROUND SOUND DATA

Audio output frame slots 6 to 9 are used to send surround sound data.

SLOTS 10 AND 11: LINE2 AND HANDSET DAC

These data slots are not supported.

SLOT 12: GPIO CONTROL

These data slots are not supported.

AC-LINK AUDIO INPUT FRAME (SDATAIN)

SYNC

BITCLK

SDATAIN

CODEC

READY

SLOT(1)

SLOT(2)

SLOT(12)

'0'

'0'

'0'

19

0

19

0

19

0

19

0

TAG PHASE

DATA PHASE

20.8

µS (48kHz)

12.288MHz

81.4ns

END OF PREVIOUS

AUDIO FRAME

TIME SLOT 'VALID' BITS

('1' = TIME SLOT CONTAINS

VALID PCM DATA)

SLOT (1)

SLOT (2)

SLOT (3)

SLOT (12)

Figure 14 AC-link Audio Input Frame

The audio input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC’97 controller. As is the case for audio output frame, each AC-link audio input frame

consists of 12, 20-bit time slots.

Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol

infrastructure.

Within slot 0 the first bit is a global bit (SDATAIN slot 0, bit 15) which flags whether the WM9707 is in

the CODEC Ready state or not. If the CODEC Ready bit is a 0, this indicates that the WM9707 is not

ready for normal operation. This condition is normal following the desertion of power on reset for

example, while the WM9707’s voltage references settle. When the AC-link CODEC Ready indicator

bit is a 1, it indicates that the AC-link and the WM9707 control and status registers are in a fully

operational state. The AC’97 controller must further probe the Powerdown Control/Status Register to

determine exactly which subsections, if any, are ready.

Prior to any attempts at putting the WM9707 into operation the AC’97 controller should poll the first

bit in the audio input frame (SDATAIN slot 0, bit 15) for an indication that the WM9707 has gone

CODEC Ready.

Once the WM9707 is sampled CODEC Ready then the next 12 bit positions sampled by the AC’97

controller indicate which of the corresponding 12 time slots are assigned to input data streams, and

that they contain valid data. Figure 14 illustrates the time slot based AC-link protocol.

There are several subsections within the WM9707 that can independently go busy/ready. It is the

responsibility of the WM9707 controller to probe more deeply into the WM9707 register file to

determine which the WM9707 subsections are actually ready.