AT89C5131A-RDTIM datasheet(78/186 Pages) ATMEL

78 / 186 page

AT89C5130A/31A-M

4337G–USB–11/06

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (Table 61). This register also contains a global

disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority lev-

els by setting or clearing a bit in the Interrupt Priority register (Table 62.) and in the

Interrupt Priority High register (Table 63). Table 60. shows the bit values and priority lev-

els associated with each combination.

Registers

The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located

at address 004BH and Keyboard interrupt vector is located at address 003BH. All other

vectors addresses are the same as standard C52 devices.

Table 60.

Priority Level Bit Values

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

IPH.x

IPL.x

Interrupt Level Priority

0 (Lowest)

011

102

3 (Highest)

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