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ATmega128

2467OS–AVR–10/06

4.

Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSC-

CAL register, the device may execute some of the subsequent instructions

incorrectly.

Problem Fix / Workaround

The behavior follows errata number 1., and the same Fix / Workaround is applicable

on this errata.

5.

IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices

are replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

Select the Device ID Register of the ATmega128 by issuing the IDCODE

instruction or by entering the Test-Logic-Reset state of the TAP controller to

read out the contents of its Device ID Register and possibly data from

succeeding devices of the scan chain. Issue the BYPASS instruction to the

ATmega128 while reading the Device ID Registers of preceding devices of

the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

ATmega128 Rev. H

1.

First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V

sion will take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Com-

parator before the first conversion.

2.

Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2

3.

Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV

register, the device may execute some of the subsequent instructions incorrectly.