Freescale Semiconductor

Product Brief

MSC7110PB

Rev. 2, 12/2005

© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.

MSC7110

Low-Cost 16-Bit DSP with DDR Controller

The MSC7110 device is a highly integrated DSP processor that contains the StarCore™ SC1400 core, 64 KB of

SRAM memory, a 16 KB ICache, an 8 KB boot ROM, a 128-channel time-division multiplexing (TDM) interface

with hardware support for

µ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host

interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and event port for

enhanced debug capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply

accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V.

Figure 1. MSC7110 Block Diagram

Boot ROM

(8 KB)

RS-232

APB

64

UART

External

Memory

Interrupts

Interrupt

HDI16

32

Host

Interface

(HDI16)

External Bus

Timers

TDM

DSP

Extended

DMA

Note: The arrows show the direction of the transfer.

Interface

Port

(32 ch)

64

32

128

32

SC1400

Core

Cache

(16 KB)

Extended

Core

Interface

Unit

Fetch

M1

SRAM

(64 KB)

64

64

128

64

TDM

PXA XB

128

64

64

PLL/Clock

PLL/Clock

Trace

Buffer

(8 KB)

to/from OCE

32

Events

32

IPBus

to DMA

to EMI

JTAG

JTAG Port

Core

AMDMA

AMIC

AMEC

ASM1

ASM2

ASEMI

ASTH

ASAPB

from

IPBus

ASSB

GPIO

GPIO

Instruction

to IPBus

Watchdog

Event Port

to Crossbar

System Control

Control

32

ASAPB

The MSC7110 device

targets high-bandwidth

highly computational

DSP applications and

is optimized for

Enterprise class packet

telephony applications,

providing a competitive

price per channel for

voice over packet

systems.