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4-58

Serial Port Timing: Shift Register Mode Test Conditions

Shift Register Mode Timing Waveforms

Note:

1.

AC inputs during testing are driven at 2.4V for a

logic “1” and 0.45V for a logic “0”. Timing measure-

ments are made at 2.0V for a logic “1” and 0.8V for a

logic “0”.

Note:

1.

For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

Max

Min

Max

Serial Port Clock Cycle Time

1.0

µs

Output Data Setup to Clock Rising Edge

700

ns

Output Data Hold After Clock Rising Edge

50

ns

Input Data Hold After Clock Rising Edge

0

0

ns

Clock Rising Edge to Input Data Valid

700

ns

t

XHDV

t

QVXH

t

XLXL

t

XHDX

t

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

0

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

SET TI

SET RI

8

VALID

VALID

VALID

VALID

VALID

VALID

VALID

VALID

0.45V

TEST POINTS

V

- 0.5V

CC

0.2 V

+ 0.9V

CC

0.2 V

- 0.1V

CC

V

LOAD

+ 0.1V

Timing Reference

Points

V

LOAD

- 0.1V

LOAD

V

V

OL

+ 0.1V

V

OL

- 0.1V