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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATMEGA640 데이터시트(PDF) 21 Page - ATMEL Corporation |
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ATMEGA640 데이터시트(HTML) 21 Page - ATMEL Corporation |
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21 / 449 page  21 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 all these addressing modes. The Register File is described in “General Purpose Regis- ter File” on page 13. Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 12. Figure 12. On-chip Data SRAM Access Cycles Table 4. Data Memory Map Address (HEX) 0 - 1F 32 Registers 20 - 5F 64 I/O Registers 60 - 1FF 416 External I/O Registers 200 Internal SRAM (8192 x 8) 21FF 2200 External SRAM (0 - 64K x 8) FFFF clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address CPU Memory Access Instruction Next Instruction |
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