ATMEGA162-16AI datasheet(5/325 Pages) ATMEL

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ATmega162/V

2513I–AVR–02/07

ATmega161 Compatibility

Mode

Programming the M161C will change the following functionality:

•

The extended I/O map will be configured as internal RAM once the M161C Fuse is

programmed.

•

The timed sequence for changing the Watchdog Time-out period is disabled. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page

57 for details.

•

The double buffering of the USART Receive Registers is disabled. See “AVR

USART vs. AVR UART – Compatibility” on page 170 for details.

•

Pin change interrupts are not supported (Control Registers are located in Extended

I/O).

•

One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers

in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be

affected by the ATmega161 compatibility fuse.

Pin Descriptions

VCC

Digital supply voltage

GND

Ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. When pins PA0 to PA7 are used as inputs and are externally

pulled low, they will source current if the internal pull-up resistors are activated. The Port

A pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Port A also serves the functions of various special features of the ATmega162 as listed

on page 73.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega162 as listed

on page 73.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running. If the JTAG interface is

enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-

vated even if a Reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the

ATmega162 as listed on page 76.

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