7

3053B–MICRO–3/05

AT89LS51

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-

tures. In that case, the reset or inactive values of the new bits will always be 0.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five

interrupt sources in the IP register.

Table 5-1.

AT89LS51 SFR Map and Reset Values

0F8H

0FFH

0F0H

B

00000000

0F7H

0E8H

0EFH

0E0H

ACC

00000000

0E7H

0D8H

0DFH

0D0H

PSW

00000000

0D7H

0C8H

0CFH

0C0H

0C7H

0B8H

IP

XX000000

0BFH

0B0H

P3

11111111

0B7H

0A8H

IE

0X000000

0AFH

0A0H

P2

11111111

AUXR1

XXXXXXX0

WDTRST

XXXXXXXX

0A7H

98H

SCON

00000000

SBUF

XXXXXXXX

9FH

90H

P1

11111111

97H

88H

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

AUXR

XXX00XX0

8FH

80H

P0

11111111

SP

00000111

DP0L

00000000

DP0H

00000000

DP1L

00000000

DP1H

00000000

PCON

0XXX0000

87H