AT89LS52-16AI datasheet(10/40 Pages) ATMEL

10 / 40 page

2601B–MICRO–03/05

AT89LS52

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K

bytes each of external Program and Data Memory can be addressed.

6.1

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89LS52, if EA is connected to VCC, program fetches to addresses 0000H through

1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are

directed to external memory.

6.2

Data Memory

The AT89LS52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel

address space to the Special Function Registers. This means that the upper 128 bytes have the

same addresses as the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used

in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR

space. Instructions which use direct addressing access of the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H

(which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the

following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at

address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data

RAM are available as stack space.

Table 5-4.

AUXR1: Auxiliary Register 1

AUXR1

Address = A2H

Reset Value = XXXXXXX0B

Not Bit Addressable

––

–

DPS

Bit

–

Reserved for future expansion

DPS

Data Pointer Register Select

DPS

Selects DPTR Registers DP0L, DP0H

Selects DPTR Registers DP1L, DP1H

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