AT43USB325 datasheet(49/109 Pages) ATMEL

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3355C–USB–4/05

AT43USB325

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are

scaled directly from the 12 MHz system clock. If the external pin modes are used for

Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an

output. This feature can give the user SW control of the counting.

6.4.3

Timer/Counter1 – TCNT1H and TCNT1L

This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that

both the high and low bytes are read and written simultaneously when the CPU accesses these

registers, the access is performed using an 8-bit temporary register (TEMP). This temporary reg-

ister is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also

interrupt routines perform access to registers using TEMP, interrupts must be disabled during

access from the main program and from interrupt routines if interrupts are allowed from within

interrupt routines.

• TCNT1 Timer/Counter1 Write:

When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register.

Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte

data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register

simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit reg-

ister write operation.

• TCNT1 Timer/Counter1 Read:

When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU

and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the

data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently,

the low byte TCNT1L must be accessed first for a full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write

access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 con-

tinues counting in the timer clock cycle after it is preset with the written value.

101

CK/1024

External Pin T1, falling edge

External Pin T1, rising edge

Table 6-4.

Clock 1 Prescale Select (Continued)

CS12

CS11

CS10

Description

Bit

$2D ($4D)

MSB

–

TCNT1H

$2C ($4C)

–

LSB

TCNT1L

Read/Write

R/W

Initial Value

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