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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89LP4052 데이터시트(PDF) 15 Page - ATMEL Corporation |
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AT89LP4052 데이터시트(HTML) 15 Page - ATMEL Corporation |
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15 / 90 page  15 3547F–MICRO–6/06 AT89LP2052/LP4052 A longer response time results if the request is blocked by one of the previously listed condi- tions. If an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final clock cycle, the additional wait time cannot be more than 3 cycles, since the longest are only 4 cycles long. If the instruction in progress is RETI or an access to IE or IP, the addi- tional wait time cannot be more than 7 cycles (a maximum of three more cycles to complete the instruction in progress, plus a maximum of 4 cycles to complete the next instruction). Thus, in a single-interrupt system, the response time is always more than 5 clock cycles and less than 13 clock cycles. See Figures 13-1 and 13-2. Figure 13-1. Minimum Interrupt Response Time Figure 13-2. Maximum Interrupt Response Time Clock Cycles INT0 IE0 15 Instruction LCALL 1st ISR Instr. Cur. Instr. Ack. Clock Cycles INT0 IE0 113 Instruction RETI 4 Cyc. Instr. LCALL 1st ISR In Ack. |
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