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AT89LP216-20PI 데이터시트(PDF) 16 Page - ATMEL Corporation

부품명 AT89LP216-20PI
상세설명  Microcontroller with 2K Bytes Flash
PDF  90 Pages
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제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT89LP216-20PI 데이터시트(HTML) 16 Page - ATMEL Corporation

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3621A–MICRO–6/06
AT89LP216 [Preliminary]
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed as shown in Figure 11-1.
At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 10-1 on page
14). The interrupt pin need not remain low for the entire time-out period.
Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0)
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure
11-2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 11-2. Interrupt Recovery from Power-down (PWDEX = 1)
11.2.2
Reset Recovery from Power-down
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in Figure 11-3. The internal clock will not be allowed
to propagate to the CPU until after the timer has timed out. The time-out period is controlled by
the Start-up Timer Fuses. (See Table 10-1 on page 14). If RST returns high before the time-out,
a two clock cycle internal reset is generated when the internal clock restarts. Otherwise, the
device will remain in reset until RST is brought high.
PWD
INT1
XTAL1
tSUT
Internal
Clock
PWD
INT1
XTAL1
Internal
Clock



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