AT89C5132-ROTIL datasheet(48/181 Pages) ATMEL

48 / 181 page

4173D–USB–02/06

AT89C5132

–

A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU and

peripherals. Program execution momentarily resumes with the instruction

immediately following the instruction that activated Power-down mode and may

continue for a number of clock cycles before the internal reset algorithm takes

control. Reset initializes the AT89C5132 and vectors the CPU to address 0000h.

Notes:

1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is

possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the

instruction immediately following the instruction that activated the Power-down mode should

not write to a Port pin or to the external RAM.

2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM

content.

11.5

Registers

Table 18. PCON Register

PCON (S:87h) – Power Configuration Register

Reset Value = 00XX 0000b

765

4321

SMOD1

SMOD0

GF1

GF0

IDL

Bit Number

Bit

Mnemonic

Description

7SMOD1

Serial Port Mode Bit 1

Set to select double baud rate in mode 1,2 or 3.

6SMOD0

Serial Port Mode Bit 0

Set to select FE bit in SCON register.

Clear to select SM0 bit in SCON register.

5 - 4

Reserved

The value read from these bits is indeterminate. Do not set these bits.

3GF1

General-Purpose Flag 1

One use is to indicate whether an interrupt occurred during normal operation or during

Idle mode.

2GF0

General-Purpose Flag 0

One use is to indicate whether an interrupt occurred during normal operation or during

Idle mode.

1PD

Power-Down Mode Bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode.

If IDL and PD are both set, PD takes precedence.

0IDL

Idle Mode Bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

If IDL and PD are both set, PD takes precedence.

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