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SY10E175JC 데이터시트(PDF) 1 Page - Micrel Semiconductor |
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SY10E175JC 데이터시트(HTML) 1 Page - Micrel Semiconductor |
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1 / 4 page ![]() 1 SY10E175 SY100E175 Micrel, Inc. M9999-032006 hbwhelp@micrel.com or (408) 955-1690 Pin Function D0 – D8 Data Inputs LEN Latch Enable MR Master Reset Q0 – Q8 Data Outputs ODDPAR Parity Output VCCO VCC to Output DESCRIPTION FEATURES s 9-bit latch s Extended 100E VEE range of –4.2V to –5.5V s Parity detection/generation s 800ps max. D to Output s Reset s Internal 75K Ω input pull-down resistors s Fully compatible with Motorola MC10E/100E175 s Available in 28-pin PLCC package The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level. 9-BIT LATCH WITH PARITY SY10E175 SY100E175 BLOCK DIAGRAM ODDPAR D0 LEN MR Q8 Q0 D8 bits 1 – 7 D EN Q R D EN Q R D EN Q R PIN NAMES Rev.: F Amendment: /0 Issue Date: March 2006 |
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