BL602/604 Datasheet

programmable breakpoints, interrupt controller including 64 interrupts and 16 interrupt levels/priorities for low latency

interrupt processing. Up to 192MHz clock frequency, can be dynamically configured to change clock frequency, enter

the power saving mode to achieve low power consumption.

Both WiFi/BLE stack and application run on single 32-bit RISC CPU for simple and ultra-low power applications. CPU

performance ~1.46 DMIPS/MHz. ~3.1 CoreMark/MHz.

2.2 Cache

BL602/BL604 cache improves CPU performance to access external memory. Cache memories can be partially or

fully configured as TCM (tightly coupled memory).

2.3 Memory

BL602/BL604 memories include: on-chip zero-delay SRAM memories, read-only memories, write-once memories,

embedded flash memory (optional).

2.4 DMA

BL602/BL604 DMA (direct memory access) controller has four dedicated channels that manage data transfer between

peripherals and memories to improve cpu/bus efficiency. There are three main types of transfers including memory to

memory, memory to peripheral, and peripheral to memory. DMA also supports LLI (link list item) that multiple transfers

are pre-defined by a series of linked lists, then hardware automatically complete all transfers according to each LLI

size and address. DMA supports peripheral UART, I2C, SPI, ADC and DAC.

2.5 Bus

BL602/BL604 bus fabric connection and memory-map summarized as follows:

Table 2.1: Bus Connection

Slave/ Master

CPU

SDIO

DMA

Crypto

Engine

Debug

SRAM

V

V

V

V

V

Peripheral

V

V

V

-

V

WiFi/BLE

V

V

V

-

V

Table 2.2: Memory Map

Module

Base Address

Size

Description

WRAM

0x42030000

112KB

Wireless SRAM memory

RETRAM

0x40010000

4KB

Deep sleep memory (Retention RAM)

BL602/604 Datasheet

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