Pin Descriptions

Pin Configuration

QFN33-16

(Top View)

MODE/SYNC

VCC

EN1

PS

AGND

FB2

1

2

3

4

12

11

10

9

EN2

FB1

Pin #

Symbol

Function

1

PS

Phase shift pin. Logic high enables the PS feature which forces the two converters

to operate 180° out of phase when both are in forced PWM mode.

2

AGND

Analog ground. Return the feedback resistive divider to this ground. See section on

PCB layout guidelines and evaluation board layout diagram.

4, 3

FB1, FB2

Feedback input pins. An external resistive divider ties to each and programs the

respective output voltage to the desired value.

5, 16

VIN1, VIN2

Input supply voltage pins. Must be closely decoupled to the respective PGND.

6, 15

N/C

Not connected

7, 14

LX1, LX2

Output switching nodes that connect to the respective output inductor.

8, 13

PGND1, PGND2

Main power ground return. Connect to the input and output capacitor return. See

section on PCB layout guidelines and evaluation board layout diagram.

10, 9

EN1, EN2

Converter enable input pins. A logic high enables the converter channel. A logic low

forces the channel into shutdown mode, reducing the channel supply current to less

than 1µA. This pin should not be left floating. When not actively controlled, this pin

can be tied directly to VIN and/or VCC.

11

VCC

Control circuit power supply. Connect to the higher voltage of VIN1 or VIN2.

12

MODE/SYNC

Logic low enables automatic light load mode for optimized efficiency throughout the

entire load range. Logic high forces low noise PWM operation under all operating

conditions. Connect to an external clock for synchronization (PWM only).

EP

Exposed paddle (bottom). Use properly sized vias for thermal coupling to the

ground plane. See section on PCB layout guidelines.

AAT2513

Dual 600mA Step-Down

Converter with Synchronization

2

2513.2007.04.1.1