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CDP6402CD 데이터시트(PDF) 12 Page - Intersil Corporation

부품명 CDP6402CD
상세설명  CMOS Universal Asynchronous Receiver/Transmitter (UART)
PDF  12 Pages
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP6402CD 데이터시트(HTML) 12 Page - Intersil Corporation

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5-85
Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF
(NOTE 1)
PARAMETERS
VDD
(V)
LIMITS
UNITS
CDP6402
CDP6402C
(NOTE 2)
TYP
(NOTE 3)
MAX
(NOTE 2)
TYP
(NOTE 3)
MAX
RECEIVER TIMING (See Figure 8)
Minimum Clock Period (RRC)
tCC
5
250
310
250
310
ns
10
125
155
-
-
ns
Minimum Pulse Width
Clock Low Level
tCL
5
100
125
100
125
ns
10
75
100
-
-
ns
Clock High Level
tCH
5
100
125
100
125
ns
10
75
100
-
-
ns
Data Received Reset
tDD
5
50755075
ns
10
25
40
-
-
ns
Minimum Setup Time
Data Start Bit to Clock
tDC
5
100
150
100
150
ns
10
50
75
-
-
ns
Propagation Delay Time
Data Received Reset to
Data Received
tDDA
5
150
250
150
250
ns
10
75
125
-
-
ns
Clock to Data Valid
tCDV
5
275
400
275
400
ns
10
110
175
-
-
ns
Clock to DR
tCDA
5
275
400
275
400
ns
10
110
175
-
-
ns
Clock to Overrun Error
tCOE
5
275
400
275
400
ns
10
100
150
-
-
ns
Clock to Parity Error
tCPE
5
240
375
240
375
ns
10
120
175
-
-
ns
Clock to Framing Error
tCFE
5
200
300
200
300
ns
10
100
150
-
-
ns
NOTES:
1. All measurements are made at the 50% point of the transition except three-state measurements.
2. Typical values for TA = 25
oC and nominal V
DD.
3. Maximum limits of minimum characteristics are the values above which all devices function.
CDP6402, CDP6402C



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