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HEF4511BDF 데이터시트(PDF) 2 Page - NXP Semiconductors |
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HEF4511BDF 데이터시트(HTML) 2 Page - NXP Semiconductors |
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2 / 11 page ![]() January 1995 2 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver HEF4511B MSI DESCRIPTION The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (DA to DD), an active LOW latch enable input (EL), an active LOW ripple blanking input (BI), an active LOW lamp test input (LT), and seven active HIGH n-p-n bipolar transistor segment outputs (Oa to Og). When EL is LOW, the state of the segment outputs (Oa to Og) is determined by the data on DA to DD. When EL goes HIGH, the last data present on DA to DD are stored in the latches and the segment outputs remain stable. When LT is LOW, all the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BI forces all segment outputs LOW. The inputs LT and BI do not affect the latch circuit. Fig.1 Functional diagram. PINNING HEF4511BP(N): 16-lead DIL; plastic (SOT38-1) HEF4511BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4511BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America DA to DD address (data) inputs EL latch enable input (active LOW) BI ripple blanking input (active LOW) LT lamp test input (active LOW) Oa to Og segment outputs Fig.2 Pinning diagram. Fig.3 Schematic diagram of output stage. FAMILY DATA, IDD LIMITS category MSI See Family Specifications Fig.4 Segment designation. |
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