전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

HEF4511BDF 데이터시트(PDF) 2 Page - NXP Semiconductors

부품명 HEF4511BDF
상세설명  BCD to 7-segment latch/decoder/driver
PDF  11 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

HEF4511BDF 데이터시트(HTML) 2 Page - NXP Semiconductors

  HEF4511BDF Datasheet HTML 1Page - NXP Semiconductors HEF4511BDF Datasheet HTML 2Page - NXP Semiconductors HEF4511BDF Datasheet HTML 3Page - NXP Semiconductors HEF4511BDF Datasheet HTML 4Page - NXP Semiconductors HEF4511BDF Datasheet HTML 5Page - NXP Semiconductors HEF4511BDF Datasheet HTML 6Page - NXP Semiconductors HEF4511BDF Datasheet HTML 7Page - NXP Semiconductors HEF4511BDF Datasheet HTML 8Page - NXP Semiconductors HEF4511BDF Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 11 page
background image
January 1995
2
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
HEF4511B
MSI
DESCRIPTION
The HEF4511B is a BCD to 7-segment
latch/decoder/driver with four address inputs (DA to DD),
an active LOW latch enable input (EL), an active LOW
ripple blanking input (BI), an active LOW lamp test input
(LT), and seven active HIGH n-p-n bipolar transistor
segment outputs (Oa to Og).
When EL is LOW, the state of the segment outputs (Oa to
Og) is determined by the data on DA to DD.
When EL goes HIGH, the last data present on DA to
DD are stored in the latches and the segment outputs
remain stable. When LT is LOW, all the segment outputs
are HIGH independent of all other input conditions. With
LT HIGH, a LOW on BI forces all segment outputs LOW.
The inputs LT and BI do not affect the latch circuit.
Fig.1 Functional diagram.
PINNING
HEF4511BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4511BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4511BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
DA to DD
address (data) inputs
EL
latch enable input (active LOW)
BI
ripple blanking input (active LOW)
LT
lamp test input (active LOW)
Oa to Og
segment outputs
Fig.2 Pinning diagram.
Fig.3 Schematic diagram of output stage.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.4
Segment
designation.



Html Pages

1 2 3 4 5 6 7 8 9 10 11


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com