LAN91C96IQFP datasheet(61/109 Pages) SMSC

61 / 109 page

Non-PCI Single-Chip Full Duplex Ethernet Controller

SMSC DS – LAN91C96I

Page 61

Rev. 03-28-07

DATASHEET

8.2

Typical Flow of Events for Transmit (Auto Release = 1)

S/W DRIVER

MAC SIDE

ISSUE ALLOCATE MEMORY FOR TX - N

BYTES - the MMU attempts to allocate N bytes

of RAM.

WAIT

FOR

SUCCESSFUL

COMPLETION

CODE - Poll until the ALLOC INT bit is set or

enable its mask bit and wait for the interrupt.

The TX packet number is now at the Allocation

Result Register.

LOAD TRANSMIT DATA - Copy the TX packet

number into the Packet Number Register. Write

the Pointer Register, then use a block move

operation from the upper layer transmit queue

into the Data Register.

ISSUE "ENQUEUE PACKET NUMBER TO TX

FIFO" - This command writes the number

present in the Packet Number Register into the

TX FIFO. The transmission is now enqueued.

No further CPU intervention is needed until a

transmit interrupt is generated.

The enqueued packet will be transferred to the

MAC block as a function of TXENA (nTCR) bit

and of the deferral process (1/2 duplex mode

only) state.

Transmit

pages

are

released

transmit

completion.

The MAC generates a TXEMPTY interrupt

upon a completion of a sequence of

enqueued packets.

If a TX failure occurs on any packets, TX

INT is generated and TXENA is cleared,

transmission sequence stops. The packet

number of the failure packet is presented at

the TX FIFO PORTS Register.

SERVICE INTERRUPT – Read Interrupt

Status Register, exit the interrupt service

routine.

Option 1) Release the packet.

Option 2) Check the transmit status in the

EPH STATUS Register, write the packet

number of the current packet to the Packet

Number Register, re-enable TXENA, then

go to step 4 to start the TX sequence again.

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