AM29F400B datasheet(16/43 Pages) AMD

16 / 43 page

Am29F400B

21505E5 November 1, 2006

D A TA

SH EE T

addresses are no longer latched. The system can

determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “The Erase Resume

command is valid only during the Erase Suspend

mode.” for information on these status bits.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

m i ng op erat io n. Th e Byt e Pr ogra m co mm an d

sequence should be reinitiated once the device has

reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Note:

See Table 5 for program command sequence.

Figure 2.

Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 shows

the address and data requirements for the chip erase

command sequence.

Any comm ands wr it ten to th e chip dur ing th e

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

device has returned to reading array data, to ensure

data integrity.

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See “The

Erase Resume command is valid only during the Erase

Suspend mode.” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the “Erase/Program Operations” tables in “AC

Characteristics” for parameters, and to Figure 14 for

timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 5 shows the address and data

requirements for the sector erase command sequence.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

AM29F400B 데이터시트(PDF) 16 Page - Advanced Micro Devices

AM29F400B 데이터시트(HTML) 16 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

데이터시트 다운로드

링크 URL