June 14, 2005

Am29LV641G

52

ADV ANCE

I N FO RMAT I O N

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1.

Typical program and erase times assume the following conditions: 25

°C, 3.0 V V

assume checkerboard pattern.

2.

Under worst case conditions of 90

°C, V

3.

The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than

the maximum program times listed.

4.

In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

5.

System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further

information on command definitions.

6.

The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except V

TSOP & FBGA PIN CAPACITANCE

Notes:

1.

Sampled, not 100% tested.

2.

Test conditions T

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.6

4

sec

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

50

sec

Word Program Time

7

210

µs

Excludes system level

overhead (Note 5)

Accelerated Word Program Time

4

120

µs

Chip Program Time (Note 3)

18

54

sec

Description

Min

Max

Input voltage with respect to V

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V

–1.0 V

V

V

–100 mA

+100 mA

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

C

IN

Input Capacitance

V

TSOP

6

7.5

Fine-pitch

BGA

4.2

5.0

C

OUT

Output Capacitance

V

TSOP

8.5

12

Fine-pitch

BGA

5.4

6.5

C

IN2

Control Pin Capacitance

V

TSOP

7.5

9

Fine-pitch

BGA

3.9

4.7

Parameter Description

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

°C

10

Years

125

°C

20

Years