AD9949 datasheet(13/36 Pages) AD

부품명	AD9949

상세설명	12-Bit CCD Signal Processor with Precision Timing Core

PDF	36 Pages

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13 / 36 page

AD9949

Rev. B | Page 13 of 36

COMPLETE REGISTER LISTING

All addresses and default values are expressed in

hexadecimal.

All registers are VD/HD updated as shown in Figure 14,

except for the registers indicated in Table 7, which are SL

updated.

Table 7. SL Updated Registers

Description

OPRMODE

AFE Operation Modes

CTLMODE

AFE Control Modes

SW_RESET

Software Reset Bit

TGCORE _RSTB

Reset Bar Signal for Internal TG Core

PREVENTUPDATE

Prevents Update of Registers

VDHDEDGE

VD/HD Active Edge

FIELDVAL

Resets Internal Field Pulse

HBLKRETIME

Retimes the HBLK to Internal Clock

CLPBLKOUT

CLP/BLK Output Pin Select

CLPBLKEN

Enables CLP/BLK Output Pin

H1CONTROL

H1/H2 Polarity/Edge Control

RGCONTROL

RG Polarity/Edge Control

DRVCONTROL

RG and H1 to H4 Drive Current

SAMPCONTROL

SHP/SHD Sampling Edge Control

DOUTPHASE

Data Output Phase Adjustment

AD9949 데이터시트(PDF) 13 Page - Analog Devices