AM29PDL640G datasheet(37/61 Pages) AMD

37 / 61 page

December 13, 2005

Am29PDL640G

D A TA SH EE T

Legend:

DYB = Dynamic Protection Bit

OW = Address (A6:A0) is (0011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A5:A0) is (001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address bits

A21:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)

WP = PPB Address (A6:A0) is (0111010) (Note 16)

EP = PPB Erase Address (A6:A0) is (1111010) (Note 16)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

See Table 1 for description of bus operations.

All values are in hexadecimal.

Shaded cells in table denote read cycles. All other cycles are

write operations.

During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

The reset command returns device to reading array.

Cycle 4 programs the addressed locking bit. Cycles 5 and 6

validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0

in cycle 6, program command must be issued and verified again.

Data is latched on the rising edge of WE#.

Entire command sequence must be entered for each portion of

password.

Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at

addresses 0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed to prevent PPB

overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

16. For all other parts that use the Persistent Protection Bit (excluding

PDL128G), the WP and EP addresses are 00000010.

17. Immediately following successful unlock, write the SecSi Sector

Exit command before attempting to verify, program, or erase the

PPBs.

18. Immediately following the PPB Lock Status command write the

SecSi Sector Exit command before attempting to verify, program,

or erase the PPBs.

Table 15.

Sector Protection Command Definitions

Command (Notes)

Bus Cycles (Notes 1-4)

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

XXX

SecSi Sector Entry

555

2AA

555

SecSi Sector Exit

555

2AA

555

SecSi Protection Bit Program (5, 6)

555

2AA

555

RD(0)

SecSi Protection Bit Status

555

2AA

555

RD(0)

Password Program (5, 7, 8)

555

2AA

555

XX[0-3]

PD[0-3]

Password Verify (8, 9)

555

2AA

555

PWA[0-3] PWD[0-3]

Password Unlock (7, 10, 11, 17)

555

2AA

555

PWA[0-3] PWD[0-3]

PPB Program (5, 6, 12)

555

2AA

555

(SA)WP

(SA)WP RD(0)

All PPB Erase (5, 13, 14)

555

2AA

555

(SA)EP

(SA)WP RD(0)

PPB Lock Bit Set

555

2AA

555

PPB Lock Bit Status (15, 18)

555

2AA

555

RD(1)

DYB Write (7)

555

2AA

555

DYB Erase (7)

555

2AA

555

DYB Status

555

2AA

555

RD(0)

PPMLB Program (5, 6, 12)

555

2AA

555

RD(0)

PPMLB Status (5)

555

2AA

555

RD(0)

SPMLB Program (5, 6, 12)

555

2AA

555

RD(0)

SPMLB Status (5)

555

2AA

555

RD(0)

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