AM29PDL127H datasheet(6/68 Pages) AMD

6 / 68 page

Am29PDL127H

June 07, 2005

P RE L I M I NARY

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Simultaneous Operation Block Diagram . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29PDL127H Device Bus Operations ...........................10

Requirements for Reading Array Data ................................... 10

Random Read (Non-Page Read) ........................................... 10

Page Mode Read .................................................................... 10

Table 2. Page Select .......................................................................11

Simultaneous Operation ......................................................... 11

Table 3. Bank Select .......................................................................11

Writing Commands/Command Sequences ............................ 11

Accelerated Program Operation ............................................. 11

Autoselect Functions .............................................................. 11

Automatic Sleep Mode ........................................................... 12

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 12

Table 4. Am29PDL127H Sector Architecture ..................................13

Table 5. SecSi

TM Sector Addresses ...............................................20

Table 6. Autoselect Codes (High Voltage Method) ........................21

Table 7. Am29PDL127H Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................22

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 23

Persistent Sector Protection ................................................... 23

Persistent Protection Bit (PPB) ............................................... 23

Persistent Protection Bit Lock (PPB Lock) ............................. 23

Dynamic Protection Bit (DYB) ................................................ 23

Table 8. Sector Protection Schemes ...............................................24

Persistent Sector Protection Mode Locking Bit ...................... 24

Password Protection Mode ..................................................... 24

Password and Password Mode Locking Bit ........................... 25

64-bit Password ...................................................................... 25

Write Protect (WP#) ................................................................ 25

Persistent Protection Bit Lock ................................................. 25

High Voltage Sector Protection .............................................. 26

Figure 1. In-System Sector Protection/

Sector Unprotection Algorithms ...................................................... 27

Temporary Sector Unprotect .................................................. 28

Figure 2. Temporary Sector Unprotect Operation........................... 28

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 28

Factory-Locked Area (64 words) ............................................ 28

Customer-Lockable Area (64 words) ...................................... 28

Figure 3. SecSi Sector Protection Algorithm................................... 29

SecSi Sector Protection Bits ................................................... 30

Figure 4. SecSi Sector Protect Verify.............................................. 30

Hardware Data Protection ...................................................... 30

Low VCC Write Inhibit ............................................................ 30

Write Pulse “Glitch” Protection ............................................... 30

Logical Inhibit .......................................................................... 30

Power-Up Write Inhibit ............................................................ 30

Common Flash Memory Interface (CFI) . . . . . . . 30

Command Definitions . . . . . . . . . . . . . . . . . . . . . 35

Reading Array Data ................................................................ 35

Reset Command ..................................................................... 35

Autoselect Command Sequence ............................................ 35

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 35

Word Program Command Sequence ...................................... 36

Unlock Bypass Command Sequence ..................................... 36

Figure 5. Program Operation ......................................................... 37

Chip Erase Command Sequence ........................................... 37

Sector Erase Command Sequence ........................................ 37

Figure 6. Erase Operation.............................................................. 38

Erase Suspend/Erase Resume Commands ........................... 38

Password Program Command ................................................ 38

Password Verify Command .................................................... 39

Password Protection Mode Locking Bit Program Command .. 39

Persistent Sector Protection Mode Locking Bit Program

Command ............................................................................... 39

SecSi Sector Protection Bit Program Command .................... 39

PPB Lock Bit Set Command ................................................... 39

DYB Write Command ............................................................. 39

Password Unlock Command .................................................. 40

PPB Program Command ........................................................ 40

All PPB Erase Command ........................................................ 40

DYB Write Command ............................................................. 40

PPB Lock Bit Set Command ................................................... 40

PPB Status Command ............................................................ 40

PPB Lock Bit Status Command .............................................. 40

Sector Protection Status Command ....................................... 40

Table 13. Memory Array Command Definitions ............................. 41

Table 14. Sector Protection Command Definitions ........................ 42

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 43

DQ7: Data# Polling ................................................................. 43

Figure 7. Data# Polling Algorithm .................................................. 43

DQ6: Toggle Bit I .................................................................... 44

Figure 8. Toggle Bit Algorithm........................................................ 44

DQ2: Toggle Bit II ................................................................... 45

Reading Toggle Bits DQ6/DQ2 ............................................... 45

DQ5: Exceeded Timing Limits ................................................ 45

DQ3: Sector Erase Timer ....................................................... 45

Table 15. Write Operation Status ................................................... 46

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 47

Figure 9. Maximum Negative Overshoot Waveform ...................... 47

Figure 10. Maximum Positive Overshoot Waveform...................... 47

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 11. Test Setup.................................................................... 49

Table 16. Test Specifications ......................................................... 49

Figure 12. Input Waveforms and Measurement Levels ................. 49

AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 50

Read-Only Operations ........................................................... 50

Figure 13. Read Operation Timings ............................................... 51

Figure 14. Page Read Operation Timings...................................... 51

Hardware Reset (RESET#) .................................................... 52

Figure 15. Reset Timings ............................................................... 52

Erase and Program Operations .............................................. 53

Figure 16. Program Operation Timings.......................................... 54

Figure 17. Accelerated Program Timing Diagram .......................... 54

Figure 18. Chip/Sector Erase Operation Timings .......................... 55

Figure 19. Back-to-back Read/Write Cycle Timings ...................... 56

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