COM20022I-HT datasheet(41/82 Pages) SMSC

41 / 82 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 41

Revision 02-27-06

DATASHEET

Table 6.7 - Address Pointer Low Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

7-0

Address 7-0

A7-A0

SWAP

These bits hold the lower 8 address bits which provide the

addresses to RAM.

When 16 bit access is enabled, (W16=1), A0 becomes the SWAP

bit. Swap bit is undefined after a hardware reset. The swap bit

must be set before W16 bit is set to “1”. The swap bit is used to

swap the upper and lower data byte. The swap bit influences

both CPU cycle and DMA cycle. See Table Below.

Detected Host Interface

Mode

Swap Bit

D15-D8

D7-D0 Pin

Intel 80xx Mode

Odd

Even

(RD, WR Mode)

Even

Odd

Motorola 68xx Mode

Even

Odd

(DIR, DS Mode)

Odd

Even

Table 6.8 - Sub Address Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

7-3

Reserved

These bits are undefined.

2,1,0

Sub Address 2,1,0

SUBAD

2,1,0

These bits determine which register at address 07 may be

accessed. The combinations are as follows:

SUBAD2

SUBAD1

SUBAD0

Tentative ID \ (Same

Node ID

\ as in

Setup 1

/ Config

Next ID

/ Register)

Setup 2

Bus Control

DMA Count

Reserved

SUBAD1 and SUBAD0 are exactly the same as exist in the

Configuration Register. SUBAD2 is cleared automatically by writing

the Configuration Register.

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