AM29SL400CB100REF datasheet(16/44 Pages) AMD

16 / 44 page

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A TA

SH EE T

Figure 2.

Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles for

programming or erasing provides data protection against in-

advertent writes (refer to Table 5 on page 18 for command

definitions). In addition, the following hardware data protec-

tion measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level

signals during VCC power-up and power-down transitions, or

from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any

write cycles. This protects data during VCC power-up and

power-down. The command register and all internal pro-

gram/erase circuits are disabled, and the device resets. Sub-

sequent writes are ignored until VCC is greater than VLKO.

The system must provide the proper signals to the control

pins to prevent unintentional writes when VCC is greater than

VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the de-

vice does not accept commands on the rising edge of WE#.

The internal state machine is automatically reset to reading

array data on power-up.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

All protected sectors unprotected.

All previously protected sectors are protected once again.

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