PCF85063ATSLASHAAZ datasheet(31/55 Pages) NXP

31 / 55 page

NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

DATA BYTE

LAST DATA BYTE

acknowledge

from PCF85063A

auto increment

memory register address

auto increment

memory register address

acknowledge

from master

slave address

read bit

0 to n data bytes

no acknowledge

aaa-004436

acknowledge

from PCF85063A

acknowledge

from PCF85063A

set register

address

read register

data

slave address

write bit

00h to 11h

STOP

For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a

repeated START (Sr).

Figure 23. Master reads after setting register address (write register address; READ data)

8.5.2.1 I2C-bus error recovery technique

Slave devices like the PCF85063A use a state machine to implement the I2C protocol and expect a certain

sequence of events to occur to function properly. Unexpected events at the I2C master can wreak havoc with

the slaves connected on the bus. However, it is usually possible to recover deterministically to a known bus

state with careful protocol manipulation.

A deterministic method to clear this situation if SDA is stuck LOW (it effectively blocks any other I2C-bus

transaction, once the master recognizes a ‘stuck bus’ state), is for the master to blindly transmit nine clocks on

SCL. If the slave was transmitting data or acknowledging, nine or more clocks ensures the slave state machine

returns to a known, idle state since the protocol calls for eight data bits and one ACK bit. It does not matter

when the slave state machine finishes its transmission; extra clocks are recognized as STOP conditions.

With careful design of the bus master error recovery firmware, many I2C-bus protocol problems can be avoided.

S/W considerations: NXP recommends customers allow for S/W reset capability to enable the bus error

recovery technique. The 9-clock pulse method as described above involves a bus-master capable of providing

such a signal.

Further comments/additional information are available in [9] and [8]"UM10204".

PCF85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.1 — 8 November 2023

31 / 55

PCF85063AT/AAZ 데이터시트(PDF) 31 Page - NXP Semiconductors

PCF85063AT/AAZ 데이터시트(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

데이터시트 다운로드

링크 URL