P90CL301 datasheet(39/92 Pages) PHILIPS

39 / 92 page

1996 Dec 11

Philips Semiconductors

Preliminary speciﬁcation

Low voltage 16-bit microcontroller

P90CL301BFH (C100)

12.1.2

UART CONTROL REGISTERS SCON0 AND SCON1

The registers SCON0 and SCON1 control UART0 and UART1 modes respectively, and contain the interrupt flags.

Table 49 UART Control Registers SCON0 and SCON1

Table 50 Description of register SCON0 and SCON1 bits

Table 51 Mode deﬁned by bits SM0 and SM1

ADDRESS

FFFF 8603H

SCON0

SM0

SM1

SM2

REN

TB8

RB8

FFFF 8607H

SCON1

BIT

SYMBOL

DESCRIPTION

7 to 6

SM0 to SM1 Mode bits; see Table 51.

SM2

Multiprocessor; enable the multiprocessor communication feature in Modes 2 and 3.

If SM2 is set the RI will not be activated if the received 9th data bit RB8 = 0. In Mode 1,

if SM2 is set the RI will not be activated if a valid stop bit is not received. In Mode 0,

SM2 should be a logic 0.

REN

Receive enable; enables serial reception; set and cleared by software.

TB8

Transmit extra bit; 9th data bit that will be transmitted in Modes 2 and 3; set and

cleared by software.

RB8

Receive extra bit; in Modes 2 and 3, RB8 is the 9th bit received. In Mode 1, if SM2 = 0,

RB8 is the stop bit which is received.

1TI

Transmit interrupt; it is set by hardware at the end of the 8th bit time in Mode 0, or

halfway through the stop bit in the other modes (except: see bit SM2). TI must be

cleared by software (cannot be set by software). By writing a logic 1 the flags stay

unchanged. In order to clear a particular flag one has to write a logic 0 to the

corresponding position and a logic 1 to the others. One should avoid to use the

instruction BCLR, which can reset accidentally several flags.

0RI

Receive interrupt; set by hardware at the end of the 8th bit time in Mode 0, or halfway

through the stop bit in the other modes (except: see SM2). RI must be cleared by

software (cannot be set by software). By writing a logic 1 the flags stay unchanged. In

order to clear a particular flag one has to write a logic 0 to the corresponding position

and a logic 1 to the others. One should avoid to use the instruction BCLR, which can

reset accidentally several flags.

SM0

SM1

MODE

DESCRIPTION

shift register; 1

⁄6 × CLK

8-bit UART; BGCLK0 and BGCLK1

9-bit UART; 1

⁄16 × CLK

9-bit UART; BGCLK0 and BGCLK1

P90CL301 데이터시트(PDF) 39 Page - NXP Semiconductors

P90CL301 데이터시트(HTML) 39 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL