TLF6372

June 1989

DM54LS73ADM74LS73A Dual Negative-Edge-Triggered

Master-Slave J-K Flip-Flops with Clear

and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs The J and

K data is processed by the flip-flops on the falling edge of

the clock pulse The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

negative going edge of the clock pulse The data on the J

and K inputs is allowed to change while the clock is high or

low without affecting the outputs as long as setup and hold

times are not violated A low logic level on the clear input

will reset the outputs regardless of the levels of the other

inputs

Connection Diagram

Dual-In-Line Package

TLF6372 – 1

Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN

See NS Package Number J14A M14A N14A or W14B

Function Table

Inputs

Outputs

CLR

CLK

J

K

Q

Q

LX

X

X

L

H

H

v

LL

H

v

HL

H

L

H

v

LH

L

H

H

v

H

H

Toggle

HH

X

X

tablished

each falling edge of the clock pulse

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A