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DM74LS73AW 데이터시트(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 DM74LS73AW
상세설명  Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
PDF  6 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DM74LS73AW 데이터시트(HTML) 3 Page - National Semiconductor (TI)

  DM74LS73AW Datasheet HTML 1Page - National Semiconductor (TI) DM74LS73AW Datasheet HTML 2Page - National Semiconductor (TI) DM74LS73AW Datasheet HTML 3Page - National Semiconductor (TI) DM74LS73AW Datasheet HTML 4Page - National Semiconductor (TI) DM74LS73AW Datasheet HTML 5Page - National Semiconductor (TI) DM74LS73AW Datasheet HTML 6Page - National Semiconductor (TI)  
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Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
VI
Input Clamp Voltage
VCC e Min II eb18 mA
b
15
V
VOH
High Level Output
VCC e Min IOH e Max
DM54
25
34
V
Voltage
VIL e Max VIH e Min
DM74
27
34
VOL
Low Level Output
VCC e Min IOL e Max
DM54
025
04
Voltage
VIL e Max VIH e Min
DM74
035
05
V
IOL e 4 mA VCC e Min
DM74
025
04
II
Input Current
Max
VCC e Max
J K
01
Input Voltage
VI e 7V
Clear
03
mA
Clock
04
IIH
High Level Input
VCC e Max
J K
20
Current
VI e 27V
Clear
60
m
A
Clock
80
IIL
Low Level Input
VCC e Max
J K
b
04
Current
VI e 04V
Clear
b
08
mA
Clock
b
08
IOS
Short Circuit
VCC e Max
DM54
b
20
b
100
mA
Output Current
(Note 2)
DM74
b
20
b
100
ICC
Supply Current
VCC e Max (Note 3)
4
6
mA
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
From (Input)
RL e 2kX
Symbol
Parameter
To (Output)
CL e 15 pF
CL e 50 pF
Units
Min
Max
Min
Max
fMAX
Maximum Clock
30
25
MHz
Frequency
tPHL
Propagation Delay Time
Clear
20
28
ns
High to Low Level Output
to Q
tPLH
Propagation Delay Time
Clear
20
24
ns
Low to High Level Output
to Q
tPLH
Propagation Delay Time
Clock to
20
24
ns
Low to High Level Output
Q or Q
tPHL
Propagation Delay Time
Clock to
20
28
ns
High to Low Level Output
Q or Q
Note 1
All typicals are at VCC e 5V TA e 25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 225V and 2125V for DM54 and
DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test
equipment
Note 3
With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded
3



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