| 전자부품 데이터시트 검색엔진 |
|
CDC706 데이터시트(PDF) 13 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
CDC706 데이터시트(HTML) 13 Page - Texas Instruments |
|
13 / 41 page ![]() www.ti.com Block Read Programming Sequence P S P SCLK SDATA A Bit 7 (MSB) Bit 6 Bit 0 (LSB) th(SDATA) tsu(SDATA) tsu(START) t(BUS) th(START) tr(SM) tr(SM) tf(SM) tf(SM) tW(SCLH) tW(SCLL) tsu(STOP) VIH(SM) VIL(SM) VIH(SM) VIL(SM) SMBus Hardware Interface 9 10 SDATA SCLK SMBHost CDC706 CBUS CBUS RP RP CDC706 SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007 1 7 1 1 8 1 1 7 1 1 S Slave Address Wr A CommandCode A Sr Slave Address Rd A 8 1 8 1 8 1 1 Byte Count N A Data Byte 0 A - - - - - Data Byte N–1 A P Figure 10. Block Read Protocol Figure 11. Timing Diagram Serial Control Interface The following diagram shows how the CDC706 clock synthesizer is connected to the SMBus. Note that the current through the pullup resistors (Rp) must meet the SMBus specifications (min 100 µA, max 350 µA). If the CDC706 is not connected to SMBus, the SDATA and SCLK inputs have to be connected with 10 k Ω resistors to VCC to avoid floating input conditions. Figure 12. SMBus Hardware Interface 13 Submit Documentation Feedback |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |