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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCA5010 데이터시트(PDF) 70 Page - NXP Semiconductors |
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PCA5010 데이터시트(HTML) 70 Page - NXP Semiconductors |
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70 / 112 page  1998 Nov 02 70 Philips Semiconductors Product specification Pager baseband controller PCA5010 Fig.45 VDD as a function of load current. VBAT = 1.2 V; L = 470 µH; SRL = 5 Ω; Co = 4.7 µF; ESR = 0.5 Ω. handbook, full pagewidth MGR141 2.25 2.20 2.15 2.10 VDD (IL) mean 4 0 8 12 16 20 IL (mA) VDD (V) HF ripple 6.22.7 VDD ADJUSTMENT VDD can be shifted in four steps by adjusting the band gap voltage. The band gap voltage is set with the two bits VBG1 and VBG0 in DCCON1 according to Table 55. Table 55 VDD adjustment VBG1 VBG0 OUTPUT VOLTAGE 00 VDD 01 VDD − 50 mV 10 VDD +50mV 11 VDD + 100 mV 6.22.8 BATTERY LOW MEASUREMENT Battery low measurement is enabled by setting the SBLI bit in DCCON0. 0.5 ms after setting SBLI to logic 1 the BLI bit in DCCON0 contains the measurement result. When BLI = 0 the battery voltage is below 1.1 V. When BLI = 1 VBAT is above 1.1 V. When SBLI = 1 VBAT is measured continuously. Setting SBLI to logic 0 disables the VBAT comparator and BLI is set to logic 1. After a reset pulse at RESETIN, SBLI is reset to logic 0. |
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