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ADC3908CSSS 데이터시트(PDF) 44 Page - Texas Instruments

부품명 ADC3908CSSS
상세설명  ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
PDF  131 Pages
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홈페이지  http://www.ti.com
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ADC3908CSSS 데이터시트(HTML) 44 Page - Texas Instruments

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Note
Hysteresis must be set to 0 in slew compare mode.
6.3.6.2.4 Comparator Event Configuration
Figure 6-26 shows the digital comparator monitor events that can be configured as triggers.
The digital comparator has two options for asserting ALERT pin: event-based or window-based monitoring.
In event-based monitorin, the ALERT pin is asserted when an event is triggered based on the comparator
configuration seen in Figure 6-27.
In window-based monitoring, the ALERT pin is only asserted when the number of event triggers recorded
in CNT_MODE_x (0x1EA) crosses the threshold set in SPI register ALERT_THRESHOLD (0x1EC-0x1ED).
Window-based monitoring is enabled in SPI register CNT_EN (0x1EA). Figure 6-28 shows an example of
window-based monitoring.
0x000
0x3FF
Samples
High threshold -
Hysteresis
Low threshold +
Hysteresis
Signal above limit
0x000
0x3FF
Samples
High threshold -
Hysteresis
Low threshold +
Hysteresis
Signal below limit
0x000
0x3FF
Samples
High threshold -
Hysteresis
Low threshold +
Hysteresis
Signal out of band
0x000
0x3FF
Samples
High threshold -
Hysteresis
Low threshold +
Hysteresis
Signal in band
Signal out of band
DWC_CH_POL = 0
DWC_CH_POL = 1
Figure 6-26. Digital Comparator Event Monitoring
ADC3910D125
SBASAD1 – DECEMBER 2023
www.ti.com
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