PCD3359AP datasheet(18/32 Pages) PHILIPS

18 / 32 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

8-bit microcontroller with DTMF

generator and 128 bytes EEPROM

PCD3359A

INTERRUPTS

8.1

Derivative interrupt

One derivative interrupt event is defined. It is controlled by

bits T2F and ET2I in the EPCR (see Tables 11 and 12).

The derivative interrupt event occurs when T2F is set. This

request is honoured under the following circumstances:

• No interrupt routine proceeds

• No external interrupt request is pending

• The derivative interrupt is enabled

• ET2I is set.

The derivative interrupt routine must include instructions

that will remove the cause of the derivative interrupt by

explicitly clearing T2F. If the derivative interrupt is not

used, T2F may directly be tested by the program.

Obviously, T2F can also be asserted under program

control, e.g. to generate a software interrupt.

8.2

Port 0 Wake-up interrupts

In addition to the external interrupt CE, the PCD3359A

contain 8 level-sensitive external interrupt sources on

Port 0. This function generates an interrupt request if any

of the enabled lines of Port 0 (P0.0 to P0.7) is pulled LOW.

Like the external interrupt (and contrary to the derivative

interrupt) the Port 0 interrupt operates also in Stop mode

and forces the CPU to exit the Stop mode.

The Port 0 Wake-up interrupts are controlled by the

Enable Port 0 Interrupt bits EPI3 to EPI0 in the

Melody and Port Interrupt Control Register MDYCON.

Pairs of Port 0 interrupts are individually enabled/disabled

via bits 4, 5, 6 and 7. For details see Section 6.1.2. As the

Port 0 interrupt is directly linked to the external interrupt, it

uses the same flag (EIF), enable instructions (EN I, DIS I)

and interrupt vector.

A Port 0 Wake-up interrupt is serviced if:

• No interrupt routine is in progress

• The external interrupt is enabled

• It’s corresponding enable bit in register MDYCON is set

to a logic 1.

If a Port 0 interrupt is to be used, the port flip-flop must first

be set to a logic 1 (set to input mode) before it’s

corresponding EPIn

bit is set.

If only a portion of the Port 0 interrupts are used, the

remaining port lines may still be used as normal I/O.

In order to configure an I/O as an input, a logic 1 must first

be written to it. If a logic 0 is written to one of these port

lines (e.g. ANL P0, 00H) while it’s corresponding interrupt

is enabled, a Port 0 interrupt will be generated.

For more details see data sheet

“PCD33xxA Family;

Section External Interrupt”.

Fig.6 Simplified External/Port 0 interrupt structure.

handbook, halfpage

MGB825

P0.6

P0.7

EPI3

P0.4

P0.5

EPI2

P0.2

P0.3

EPI1

P0.0

P0.1

EPI0

CE/T0 (1)

to CE/T0 input of

Digital filter/latch of the

Interrup logic section (2)

(1) From pin CE/T0.

(2) See the

“PCD33XXA Family” data sheet.

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