W39V080FA

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After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6

toggles for about 100

μS, and then returns to reading array data. If not all selected sectors are

protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors which are protected.

The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively

erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls

within a protected sector, DQ6 toggles for about 1

μs after the program command sequence is written,

and then returns to reading array data.

6.10.4 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not

successfully completed.

The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously

programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the

device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”

Under both these conditions, the system must hardware reset to return to the read mode.

6.11 Identification Input pin ID[3:0]

These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot

device should be 0000b. And all the subsequent parts should use the up-count strapping.

6.12 Register

There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock

Control Registers and Product Identification Registers. Users can access these registers through

respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.

6.12.1 General Purpose Inputs Register

This register reads the FGPI[4:0] pins on the W39V080FA.This is a pass-through register which can

read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.

GPI Register Table

BIT

FUNCTION

7

− 5

Reserved

4

Read FGPI4 pin status

3

Read FGPI3 pin status

2

Read FGPI2 pin status

1

Read FGPI1 pin status

0

Read FGPI0 pin status

6.12.2 Block Locking Registers

This part provides 16 even 64Kbytes blocks, and each block can be locked by register control. These

control registers can be set or clear through memory address. Below is the detail description.