1999 Jan 08

22

Philips Semiconductors

Product specification

Enhanced Pager Decoder for

APOC1/POCSAG

PCD5002A

8.30

Status/control register

The status/control register consists of two independent registers, one for reading (status) and one for writing (control).

The status register shows the current operating condition of the decoder and the cause(s) of an external interrupt.

The control register activates/deactivates certain functions. Tables 17 and 18 show the bit allocations of both registers.

All status bits will be reset after a status read operation except for the out-of-range, battery-low and receiver enable

indicator bits (see note 1 to Table 17).

Table 17 Status register (00H; read)

Note

1. After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is

pending. D2 is reset when the RAM is empty (read and write pointers equal).

Table 18 Control register (00H; write)

VALUE

DESCRIPTION

D1 and D0

0 0

no new call data

0 1

new call received (POCSAG or APOC1)

1 0

continuous decoding data available

1 1

batch zero data available (APOC1)

D3 and D2

0 0

no data to be read (default after reset)

0 1

RAM read/write pointers different; data to be read

1 0

RAM read/write pointers equal; no more data to read

1 1

RAM buffer full or overflow

D4

1

alert time-out expired

D5

1

out-of-range

D6

1

BAT input HIGH or RXE output active (selected by control bit D2)

D7

1

periodic timer interrupt

BIT (MSB: D7)

VALUE

DESCRIPTION

D0

1

forced call termination (automatically reset after termination)

D1

1

EEPROM programming enable

D2

0

BAT input selected for monitoring (status bit D6)

1

RXE output selected for monitoring (status bit D6)

D3

1

receiver continuously enabled (RXE = 1 and ROE = 1)

D4

0

decoder in OFF status (while DON = 0)

1

decoder in ON status

D5

1

out-of-range interrupt masked

D6

1

BAT/RXE monitor interrupt masked

D7

1

Periodic Timer interrupt masked