1999 Jan 08

21

Philips Semiconductors

Product specification

Enhanced Pager Decoder for POCSAG

PCD5003A

7.33

Received call delay

Call reception causes both the periodic interrupt modulus and the counter register to be reset.

Since the periodic interrupt counter runs for another 2.55 seconds after a reset, the received call delay

Table 18 Alert set-up register (04H; write)

Note

1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address code-word, which designate the

POCSAG call type as shown in Table 1.

BIT (MSB: D7)

VALUE

DESCRIPTION

D0

0

call alert via cadence register

1

POCSAG call alert (pattern selected by D7, D6)

D1

0

LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)

1

HIGH level acoustic alert (ATL + ATH), continuous vibrator alert

D2

0

normal alerts (acoustic and LED)

1

D3

1

acoustic alerts enable (ATL, ATH)

D4

1

vibrator alert enabled (VIB)

D5

1

LED alert enabled (LED)

0 0

POCSAG alert pattern FC = 00, see Fig.9(a)

0 1

POCSAG alert pattern FC = 01, see Fig.9(b)

1 0

POCSAG alert pattern FC = 10, see Fig.9(c)

1 1

POCSAG alert pattern FC = 11, see Fig.9(d)

Fig.9 POCSAG alert patterns.

handbook, full pagewidth

MLC251

(a)

(b)

(c)

(d)

0 0

D7, D6

0 1

1 0

1 1