1997 Jun 24

28

Philips Semiconductors

Product specification

Advanced POCSAG Paging Decoder

PCD5003

Table 27 Identifier bit allocation

Notes

1. The bit numbering corresponds with the numbering in a POCSAG codeword: bit 1 is the flag bit

(0 = address, 1 = message).

2. A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0; bits 2 to 19 contain

the identifier bit pattern; they are followed by 2 predetermined random (function) bits and the UPSW is completed by

10 CRC error correction bits and an even-parity bit.

3. Bits FR3 to FR1 (MSB: FR3) contain the 3 least significant bits of the 21-bit RIC.

4. Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0.

BYTE

BIT (MSB: D7)

DESCRIPTION

1

D7 to D0

bits 2 to 9 of POCSAG codeword (RIC or UPSW); notes 1 and 2

2

D7 to D0

bits 10 to 17

3

D7 and D6

bits 18 and 19

D5

frame number bit FR3 (RIC); note 3

D4

frame number bit FR2 (RIC)

D3

frame number bit FR1 (RIC)

D2

identifier type selection (0 = UPSW, 1 = RIC); note 4

D1

identifier enable (1 = enabled)

D0

reserved for future use, logic 0 when read

7.57

Voltage doubler

An on-chip voltage doubler provides an unregulated DC

output for supplying an LCD or a low power microcontroller

100 nF is required between pins CCN and CCP. The

voltage doubler is enabled via SPF programming.

7.58

Level-shifted interface

All interface lines are suited for communication with a

microcontroller operating from a higher supply voltage.

of the PCD5003.

The reference voltage for the level-shifted interface must

has a separate (regulated) supply this separate supply

The level-shifted interface lines are: RST, DON, ALC,

REF, INT.

standard external pull-up resistors.

7.59

Signal test mode

A special ‘signal test’ mode is available for monitoring the

performance of a receiver circuit together with the

front-end of the PCD5003.

For this purpose the output of the digital noise filter and the

recovered bit clock are made available at outputs REF and

INT respectively. All synchronization and decoding

functions are normally active.

The ‘signal test’ mode is activated/deactivated by SPF

programming.