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PCD5091 데이터시트(PDF) 7 Page - NXP Semiconductors

부품명 PCD5091
상세설명  DECT baseband controller
PDF  16 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCD5091 데이터시트(HTML) 7 Page - NXP Semiconductors

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1997 Jul 21
7
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5091
5.2
Pin description
Table 1
QFP100 and LQFP100 packages
SYMBOL
PIN
I/O
STATE
AFTER
RESET
PIN TYPE
PIN DESCRIPTION
QFP100 LQFP100
ANT_SW1
1
99
O
H
ISP2DRF3
antenna switch 1 output
ANT_SW0
2
100
O
H
ISP2DRF3
antenna switch 0 output
CLK100
3
1
O
H
ISP2DPES
100 Hz signal related to DECT frame timing
output
T_ENABLE
4
2
O
H
ISP2DRF3
enable transmitter output
T_PWR_RMP
5
3
O
L
ISP2DRF3
switch transmitter power output
T_DATA
6
4
O
off
ISF2DRF3
unmodulated transmitter data output
T_GMSK
7
5
O
L
ANAIOD1
GMSK modulated transmitter data output
VCO_BND_SW
8
6
O
L
ISP2DRF3
VCO band switch output
SYNTH_LOCK
9
7
I
−
DIPP0RF3
synthesizer lock input
S_ENABLE
10
8
O
L
ISP2DRF3
synthesizer enable output
S_DATA
11
9
O
L
ISP2DRF3
serial synthesizer data output
S_CLK
12
10
O
L
ISP2DRF3
clock for serial synthesizer interface output
S_PWR
13
11
O
H
ISP2DRF3
switch synthesizer power output
REF_CLK
14
12
O
running
ISP4DRF3
13.824 MHz reference clock for synthesizer
output
VSS1
15
13
−−
supply
negative supply voltage 1
VDD_RF
16
14
−−
supply
positive supply voltage for RF interface level
shifters
VDD3V_1
17
15
−−
supply
positive supply voltage 1 (+3 V)
SLICE_CTR
18
16
O
L
ISP2DRF3
switch slicer time constant output
R_PWR
19
17
O
H
ISP2DRF3
switch receiver power output
R_DATAP
20
18
I
−
ANAIOD2
positive input for receiver data
R_DATAM
21
19
I
−
ANAIOD2
negative input for receiver data
R_ENABLE
22
20
O
H
ISP2DRF3
enable receiver output
RSSI_AN
23
21
I
−
ANAIOD1
analog input for RSSI measurement
VANLI
24
22
I
−
ANAIOD1
analog input to ADC
VBAT
25
23
I
−
ANAIOD1
analog input for battery voltage
measurement
CLK3
26
24
O
L
ISP2DPES
3.456 MHz clock output for external ADPCM
codec



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