1997 Nov 19

6

Philips Semiconductors

Objective specification

DECT baseband controller

PCD5095

5.2

Pin description

Table 1

QFP100 package

SYMBOL

PIN

I/O

STATE

AFTER

RESET

PIN TYPE

PIN DESCRIPTION

ANT_SW1

1

O

H

ISP2DRF3

antenna switch 1 output

ANT_SW0

2

O

H

ISP2DRF3

antenna switch 0 output

CLK100

3

O

H

ISP2DPES

100 Hz signal related to DECT frame timing output

T_ENABLE

4

O

H

ISP2DRF3

enable transmitter output

T_PWR_RMP

5

O

L

ISP2DRF3

switch transmitter power output

T_DATA

6

O

off

ISF2DRF3

unmodulated transmitter data output

T_GMSK

7

O

L

ANAIOD1

GMSK modulated transmitter data output

VCO_BND_SW

8

O

L

ISP2DRF3

VCO band switch output

SYNTH_LOCK

9

I

−

DIPP0RF3

synthesizer lock input

S_ENABLE

10

O

L

ISP2DRF3

synthesizer enable output

S_DATA

11

O

L

ISP2DRF3

serial synthesizer data output

S_CLK

12

O

L

ISP2DRF3

clock for serial synthesizer interface output

S_PWR

13

O

H

ISP2DRF3

switch synthesizer power output

REF_CLK

14

O

running

ISP4DRF3

13.824 MHz reference clock for synthesizer output

15

−−

supply

negative supply voltage 1

16

−−

supply

positive supply voltage for RF interface level shifters

17

−−

supply

positive supply voltage 1 (+3 V)

SLICE_CTR

18

O

L

ISP2DRF3

switch slicer time constant output

R_PWR

19

O

H

ISP2DRF3

switch receiver power output

R_DATAP

20

I

−

ANAIOD2

positive input for receiver data

R_DATAM

21

I

−

ANAIOD2

negative input for receiver data

R_ENABLE

22

O

H

ISP2DRF3

enable receiver output

RSSI_AN

23

I

−

ANAIOD1

analog input for RSSI measurement

VANLI

24

I

−

ANAIOD1

analog input to ADC

VBAT

25

I

−

ANAIOD1

analog input for battery voltage measurement

CLK3

26

O

L

ISP2DPES

3.456 MHz clock output for external ADPCM codec

DCK

27

I/O

input

ISF2DPES

ISF2UPES

(ISF2UPES in PCD5090/xxx, PCA5097/xxx)

DI

28

I

−

DIPP0PES

FS1

29

I/O

input

ISF2DPES

ISF2UPES

8 kHz framing input/output

(ISF2UPES in PCD5090/xxx, PCA5097/xxx)

DO

30

O

off

ISI8DPES

XTAL2

31

O

running

ANAIOD1

crystal oscillator output

XTAL1

32

I

−

ANAIOD1

crystal oscillator input

VANLO

33

O

1.0 V

ANAIOD1

analog output from DAC

34

−−

supply

negative supply voltage for the oscillator

35

−−

supply

positive supply voltage for the oscillator