©NEC Electronics Corporation 2004

78K0/KF2

ZUD-CC-04-0129-E

Data Published Oct 2004 N CP(K)

High-Speed System Clock (Crystal/Ceramic) Oscillator Characteristics

(TA = -40 to +85

°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD= EVDD, VSS = EVSS = AVSS = 0 V)

Resonator

Recommended

Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

4.0 V

≤ VDD ≤ 5.5 V

2.0

20.0

2.7 V

≤ VDD < 4.0 V

2.0

10.0

Ceramic

resonator

C1

X2

X1

VSS

C2

Oscillation

frequency(fXH)

Note

1.8 V

≤ VDD < 2.7 V

2.0

5.0

MHz

4.0 V

≤ VDD ≤ 5.5 V

2.0

20.0

2.7 V

≤ VDD < 4.0 V

2.0

10.0

Crystal resonator

Oscillation

frequency(fXH)

Note

1.8 V

≤ VDD < 2.7 V

2.0

5.0

MHz

Note

Indicates only oscillator characteristics.

Refer to AC Characteristics for instruction execution time.

Cautions 1.

When using the high-speed system clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2.

Since the CPU is started by the Ring-OSC after reset is released, check the oscillation stabilization

time of the high-speed system clock using the oscillation stabilization time status register (OSTC).

Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time

select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator

to be used.

Remark

For the resonator selection and oscillator constant, customers are requested to either

evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.

C1

X2

X1

C2

VSS