SC16C652BIB48 datasheet(13/43 Pages) NXP

13 / 43 page

NXP Semiconductors

SC16C652B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/

decoder

CTSA, CTSB

TRANSMIT

FIFO

REGISTERS

TXA, TXB

RECEIVE

SHIFT

RECEIVE

FIFO

REGISTERS

RXA, RXB

SC16C652B

TRANSMIT

SHIFT

XTAL2

XTAL1

002aaa594

FLOW

CONTROL

LOGIC

DATA BUS

AND

CONTROL

LOGIC

SELECT

LOGIC

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

MODEM

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

RTSA, RTSB

DSRA, DSRB

DTRA, DTRB

RIA, RIB

(OP1A, OP1B)

CDA, CDB

(OP2A, OP2B)

ENCODER

DECODER

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

D0 to D7

IOR

IOW

RESET

A0 to A2

CSA

CSB

Figure 5. Internal loopback mode diagram

6.11 Sleep mode

Sleep mode is an enhanced feature of the SC16C652B UART. It is enabled when EFR[4], the enhanced

functions bit, is set

and when IER[4] of both channels are set. Sleep mode is entered when:

• Modem input pins are not toggling.

• The serial data input line, RX, is idle (logic HIGH).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these

clocks, the power consumption is greatly reduced.

SC16C652B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.0 — 2 November 2023

13 / 43

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