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MGL967

TEST MODE DECODER

POWER-ON-RESET

SEQUENCER

ADDRESS

HIGH

REGISTER

BYTE

COUNTER

DIVIDER

(

128)

EE

CONTROL

TIMER

(

16)

EEPROM

ADDRESS

POINTER

BYTE

LATCH

(8 bytes)

SHIFT

REGISTER

ADDRESS

SWITCH

INPUT

FILTER

OSCILLATOR

8

4

3

n

PCF85102C-2;

PCF85103C-2

4

VSS

7

n.c.

A1

A2

A0

3

2

1

8

VDD

6

5

SCL

SDA

Fig.1 Block diagram.

The pin numbers in this block diagram refer to the PCF85102C-2.

For PCF85103C-2, please see Chapter 7.